C block delay, gate signal delay

I implemented SVPWM and Tdead using C block code
But I have some problem. When I switch on Gate signal to IGBT, the switch have delay which is same with simulation time step. Is it normal?

If I change some input values which are applied to C block, the output delay is generated which is same with simulation time step too.

Does PSIM consider device and code propagation delay?

I found that Delay occurs when I use voltage sensor.
If I connect voltage probe directly to Gate and output voltage, the timing is same.
Unlike using voltage sensor, It is OK.

But C block delay is not solved.

Hi Jaehak,

You need to be using the ZOH and 1/Z blocks from the digital control module. These blocks are crucial to properly mimic the execution of an interrupt routine on an MCU or DSP.

The ZOH block will force the signal path it is on to only execute at the rate of the ZOH, if there is a c block it will force that c block to execute at that rate independent of the simulation timestep.

The 1/z will mimic the impact of a DSP executing an interrupt routine and only being able to update the duty cycle of the pwm duty cycle at the start of the next period. This delay modelling is THE MOST IMPORTANT THING to insert into you circuit to properly simulate a digital control loop.

I have made a demo circuit so that you can see the impact of the ZOH.

the c blocks are setup to +1 each time they execute and to output the result. We can see the with the leading ZOH only executes at the ZOH rate.

The resistor with the ac source is there to force the time step to execute at our desired rate, without it the PSIM engine will optimize the simulation to run at the period of the ZOH, since there is no need to run at a small time step.