Implementing SPI AD7928 ADC block in PSIM inverter simulation

I’m simulating a three phase inverter based on a power electronic board that has been designed. The board has one external adc(AD7928) that received the feedback signals of the inverter three-phase line currents, the output load current, and the buck and boost input currents. The SPI signals are then sent to the F28335 dsp (see attached word document).

I’ve modelled the system in PSIM but I’m confused about setting some of the parameters in the SPI blocks. I went through the tutorial twice and I just need some confirmation that my SPI implementation is correct. I’m a bit confused about the start initial command value, received data command, data bit position, SPI initial command value in the SPI input block parameters. I read the data sheet several times and I’m probably interpreting it incorrectly.

To access data from this particular SPI adc I would have to write to the control registers(don’t know how to do that). I’ve attached the psim file. Any feedback would be greatly appreciated

Hi Nadia,

The first thing I see is that the SPI signals are being mapped to the ADC this is not correct. The F82335 ADC element is only needed if you are processing that signal with the on-chip ADC for the F28335. You are using the AD7928 for the conversion these signals can map from the SPI directly into you control algorithm.

The timing diagram for figure 29 shows a lot of information, because the conversion data is output at the same time that DIN is read for the last DIN address defined, we need to be careful with the how things are declared. In SPI initial you need to define the first channel to be sampled. In the receiving data command in the first channel you need to setup the second channel, which needs to setup the third channel. The third channel will then point back to the 1st channel

According to the datasheet information of AD7928, the
parameters are defined as below:

  • Chip Select Pins: depends on your hardware
  • Communication Speed (MHz): defined by signal on SCLK can be as high as 20MHz
  • Clock Type: “falling edge without delay” - figure 29 page 25
  • Command Word Length: 16 bits - figure 29
  • Sync. Active Mode: falling edge (likely don’t care)
  • SPI Initial Command: Table 7 page 14 shows how this word gets built. These bits need to be setup properly based on the data type you need and what you are trying to do. You need to declare the address of the first channel to be read here (tabvle 8)
  • Hardware Interrupt Mode: no hardware interrupt (this chip does not have an end of conversion pin)
  • Interrupt Timing: no interrupt (this chip does not have an end of conversion pin)
  • Command Gaps (ns): 0
  • Conversion Sequence: it looks like you want to convert three signals with this chip you will list the order here. The names need to match the SPI input elements (case sensitive)

SPI Input

  • Device Name: “AD7928_CH?” matches the conversion sequence name and ? is the channel you are going to use.
  • Start Conversion Command: None
  • Receiving Data Command: 0x?0, 0x00 - table 8 on page 15 will give what ? should be, the address of the channel you want the result for next. This is important, you need to point to the next channel here!
  • Data Bit Position: y=x0[3…0]x1[7…0] - the lower 12 bits contain the output information page 11 table 6
  • Input Range: The ADC range from your hardware
  • Scale Factor: scales the result, based on the received data and the defined input range
  • ADC Mode: DC or AC signal?
  • Initial Value: 0 - Do you want an initial value present?